Angsuman Roy

I didn't design any of the circuits on this chip but I did the final layout, added decoupling capacitors and designed a padframe.

I also learned a lot about picking a good package and sending the bare dies to get wirebonded by a company. Ideally we would have wirebonded these chips ourselves but we didn't have our wirebonding facility set up at UNLV at the time. Due to this, I designed the pad to be large at 150 um by  90 um so that they would be easy to wirebond by hand.

The chip has a skinny rectangle shape because we wanted to maximize the 5 sq. mm of area that we were allotted. There are a total of 38 pads and the vendor suggested that I use a CLCC-40 package. This was a bad choice because it is an extremely rare package and no one makes a socket for it. I got a quote back from a company that it would be $250 each for a socket if I ordered 100! The PLCC-44 package is very common and is used in order motherboards for the BIOS chip. In the end I had an undergraduate student researcher (Mario Verduzco) design a PCB footprint for the CLCC-40 package. The moral of this story is pick your packages carefully!