Angsuman Roy
1. A Low-Power Switched-Capacitor Passive Sigma-Delta Modulator
This paper improves upon a previous work by replacing passive RC components with switched capacitors. The performance is quite good despite being fabricated in a 500 nm CMOS process. This paper was presented at DCAS 2015.
2. An FPGA Based Passive K-Delta-1-Sigma Modulator
This paper describes a K-Delta-1-Sigma Modulator implemented entirely with an FPGA and external passive RC components. The KD1S design uses sequentially phase shifted clocks to increase the effective sampling rate. This paper was presented at the 2015 MWSCAS. The topology was invented by Dr. R. Jacob Baker and extensively implemented by Dr. Vishal Saxena. More information on this type of ADC can be found at the links below:
3. A Passive 2nd-Order Sigma-Delta Modulator for Low-Power Analog-to-Digital Conversion
This paper describes the first implementation of my passive 2nd-order sigma-delta topology detailed in my thesis. The performance of this circuit is decent but since it was my first IC design there was much room for optimization and improvement. This paper was presented at the 2014 MWSCAS.
I currently have three conference proceeding publications.