Switched Capacitor Sigma-Delta Modulator and KD1S Modulator in 500 nm CMOS (2015)

This chip improves upon the design of my continuous time sigma-delta modulator by replacing the resistors with switched capacitors. This results in zero static power consumption (except leakage). I also optimized the design of the comparator and non-overlapping clock generator to reduce total current consumption to 3.3 uA @ 2.5 V supply resulting in just 6.75 uW power dissipation. The modulator offers an effective resolution of 9.3 bits for a 3 KHz signal bandwidth using a clock frequency of 1.024 MHz. More details are found in my thesis. 

There is also a KD1S implementation that I did for fun to see how well it would perform. It's a large design and contains 760 transistors, although most of that is due to the fact that there are eight of each component. I tried to keep power consumption low by using a passive switched capacitor integrator. However, so much power is consumed by the clock generator and logic that it would have been better to use an active integrator and gain a significant increase in resolution.

Angsuman Roy